In general, some semiconductor devices entail a wiring pattern where two or more metal wires are arranged side by side. Such a wiring pattern is used, for example, for a word line on a memory cell in a semiconductor device, such as a memory. Usually the metal wiring is designed so as to cover a specific width, so that all spaces between metal wires are widened to some extent.
FIG. 1 shows a sectional view of the wiring pattern on the conventional memory cell.
As shown in FIG. 1, the first passivation layer 2, i.e. a surface protective layer, is formed on a metal wire 1 in order to prevent deterioration due to humidity in the open air. For example, this first passivation layer 2 is formed in an about 0.4 .mu.m thickness by PSG. Further, the second passivation layer 3 is formed on the first passivation layer 2 in an about 0.55 .mu.m thickness by P (plasma)-SiN. Furthermore, an about 5 .mu.m thick protective layer, such as of polyamide, is formed on the second passivation layer 3.
FIG. 1 shows a case where a metal wiring design rule allows the side to side configuration to spread. In this semiconductor device, the wiring pattern was not so much refined, because the wire to wire space was designed relatively wide. If this case was compared to the passivation layer thickness, the wiring space to the adjacent metal wire 1 is so wide that the passivation layers on the metal wire 1 could not touch each other.
However, in recent years when semiconductor devices have been increasingly refined and micro-miniaturized, the stricter design rule must be established. In other words, sometimes passivation layers on adjacent metal wires can touch each other, because the design tends toward a narrower wire to wire space width.
It is considered that such passivation layers touching causes void portions to occur at the touching points.
FIG. 2 shows a pattern for the conventional metal wiring layer in a semiconductor substrate. As illustrated in FIG. 2, the wire to wire spacing on the metal wire 1 includes wider and narrower portions due to contacts, and a 0.9.+-.0.1 .mu.m width. The metal wire 1 itself is also about 0.9.+-.0.1 .mu.m wide. As shown in FIG. 2, numeric values are examples of metal wire width and wire to wire spacing (.mu.m in unit).
FIG. 3 shows a sectional view of the semiconductor device at a wiring pattern A-A' shown in FIG. 2. This semiconductor device has a structure closely similar to the structure shown in FIG. 1. However, the semiconductor device design must be highly refined, due to the narrower wire to wire spacing between metal wires. Metal wire 1 is about 0.9.+-.0.1 .mu.m wide and 0.8 to 0.9 .mu.m thick. The first passivation layer 2, a surface protective layer, is formed on metal wire 1 to about 0.3 to 0.4 .mu.m thickness above the wire. Further, the second passivation layer 3 is formed on the first passivation layer 2 to about 0.55 .mu.m thickness above the first layer. Furthermore, a protective layer of e.g. polyamide is formed on the second passivation layer 3 to about 5 .mu.m thickness.
Accordingly, the passivation layer covering each metal wire is about 0.6 .mu.m wide, while the wire to wire spacing to the adjacent metal wires is about 0.9.+-.0.1 .mu.m. As a result, the adjacent portions of the second passivation layer 3 will overlap each other. Furthermore, since the first and second passivation layers 2 and 3 are formed on the metal wire 1 in an overhanging state, void portion 4 is formed between metal wires. The void portion 4 forms in a straw-like shape, if a semiconductor device for a memory includes the long metal wire 1.
As described above, such a void portion 4 occurs in a series of semiconductor device manufacturing processes, when the protective layer is formed after the formation of the metal wire 1. In the next padding, drilling, and mask matching processes, enclosed gas will thermally expand in a straw-like void portion 4 due to heating, such as photoresist baking and annealing.
As a result, the gas in the void portion 4 will burst out at both ends of the straw-like shape or the openings, so that photoresist foaming and so on can occur, which causes damage to the protective layers. If an escape hole is drilled in order to prevent such trouble, a special process therefor must be provided, which will reversibly affect efficiency.